2.5v or 3.3v, 200-mhz, 14 output zero delay buff er cy2977 5 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07480 rev. ** revised april 28, 2003 775 features ? output frequency range: 8.3 mhz to 200 mhz input frequency range: 4.2 mhz to 125 mhz 2.5v or 3.3v operation split 2.5v/3.3v outputs 14 clock outputs: drive up to 28 clock lines 1 feedback clock output 2 lvcmos reference clock inputs 150 ps max output-output skew pll bypass mode spread aware? output enable/disable industrial temperature range: ?40c to +85c 52-pin 1.0-mm tqfp package description the cy29775 is a low-voltage high-performance 200-mhz pll-based zero delay buffer designed for high-speed clock distribution applications. the cy29775 features two reference clock inputs and pro- vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. bank a and bank b divide the vco output by 4 or 8 while bank c divides by 8 or 12 per sel(a:c) settings, see functional table . these dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. each lvcmos compatible out- put can drive 50 ? series or parallel terminated transmission lines. for series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:28. the pll is ensured stable given that the vco is configured to run between 200 mhz to 500 mhz. this allows a wide range of output frequencies from 8.3 mhz to 200 mhz. for normal operation, the external feedback input, fb_in, is connected to the feedback output, fb_out. the internal vco is running at multiples of the input reference clock set by the feedback di- vider, see frequency table. when pll_en is low, pll is bypassed and the reference clock directly feeds the output dividers. this mode is fully static and the minimum input clock frequency specification does not apply. block diagram pin configuration pll 200 - 500mhz 2 / 4 4 / 6 / 8 / 12 qa0 qb0 qc0 fb_out sela vco_sel(1,0) tclk0 tclk_sel fb_in selb selc mr#/oe fb_sel(1,0) tclk1 2 clk stop 2 / 4 clk stop 4 / 6 clk stop clk_stp# qa1 qa2 qa3 qa4 qb1 qb2 qb3 qb4 qc1 qc2 qc3 pll_en 4 vss mr#/oe clk_stp# selb selc pll_en sela tclk_sel tclk0 tclk1 vco_sel1 vdd avdd vddqa qa0 vss qa1 vddqa qa2 fb_sel1 vss qa3 vddqa qa4 avss fb_sel0 qb0 vddqb nc vss qc3 vddqc qc2 vss qc1 vddqc qc0 vss vco_sel0 vss qb1 vddqb qb2 vss qb3 vddqb qb4 fb_in vss fb_out vddfb nc 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 cy29775
cy2977 5 document #: 38-07480 rev. ** page 2 of 10 notes: 1. pu = internal pull-up, pd = internal pull-down 2. a 0.1- f bypass capacitor should be placed as close as possible to each positive power pin (<0.2?). if these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. avdd and vdd pins must be connected to a power supply level that is at least equal or higher than that of vddqa, vddqb, vddqc , and vddfb power supply pins. pin description [1] pin name i/o type description 9 tclk0 i, pd lvcmos lvcmos/lvttl reference clock input 10 tclk1 i, pu lvcmos lvcmos/lvttl reference clock input 16, 18, 21, 23, 25 qa(4:0) o lvcmos clock output bank a 32, 34, 36, 38, 40 qb(4:0) o lvcmos clock output bank b 44, 46, 48, 50 qc(3:0) o lvcmos clock output bank c 29 fb_out o lvcmos feedback clock output . connect to fb_in for normal operation. 31 fb_in i, pu lvcmos feedback clock input . connect to fb_out for normal operation. this input should be at the same voltage rail as input reference clock. see table 1 . 2 mr#/oe i, pu lvcmos output enable/disable input . see table 2 . 3 clk_stp# i, pu lvcmos clock stop enable/disable input . see table 2 . 6 pll_en i, pu lvcmos pll enable/disable input . see table 2 . 8 tclk_sel i, pd lvcmos reference select input . see table 2 . 11, 52 vco_sel(1,0) i, pd lvcmos vco divider select input . see tables 2, 3 and 4. 7, 4, 5 sel(a:c) i, pd lvcmos frequency select input, bank (a:c) . see table 3 . 20, 14 fb_sel(1,0) i, pd lvcmos feedback dividers select inputs . see table 4 . 17, 22, 26 vddqa supply vdd 2.5v or 3.3v power supply for bank a output clocks [2,3] 33, 37, 41 vddqb supply vdd 2.5v or 3.3v power supply for bank b output clocks [2,3] 45, 49 vddqc supply vdd 2.5v or 3.3v power supply for bank c output clocks [2,3] 28 vddfb supply vdd 2.5v or 3.3v power supply for feedback output clock [2,3] 13 avdd supply vdd 2.5v or 3.3v power supply for pll [2,3] 12 vdd supply vdd 2.5v or 3.3v power supply for core and inputs [2,3] 15 avss supply ground analog ground 1, 19, 24, 30, 35, 39, 43, 47, 51 vss supply ground common ground 27, 42 nc no connection
cy2977 5 document #: 38-07480 rev. ** page 3 of 10 table 1. frequency table feedback output divider vco input frequency range (avdd = 3.3v) input frequency range (avdd = 2.5v) 8 input clock * 8 25 mhz to 62.5 mhz 25 mhz to 50 mhz 12 input clock * 12 16.6 mhz to 41.6 mhz 16.6 mhz to 33.3 mhz 16 input clock * 16 12.5 mhz to 31.25 mhz 12.5 mhz to 25 mhz 24 input clock * 24 8.3 mhz to 20.8 mhz 8.3 mhz to 16.6 mhz 32 input clock * 32 6.25 mhz to 15.625 mhz 6.25 mhz to 12.5 mhz 48 input clock * 48 4.2 mhz to 10.4 mhz 4.2 mhz to 8.3 mhz 4 input clock * 4 50 mhz to 125 mhz 50 mhz to 100 mhz 6 input clock * 6 33.3 mhz to 83.3 mhz 33.3 mhz to 66.6 mhz 8 input clock * 8 25 mhz to 62.5 mhz 25 mhz to 50 mhz 12 input clock * 12 16.6 mhz to 41.6 mhz 16.6 mhz to 33.3 mhz table 2. function table (configuration controls) control default 0 1 tclk_sel 0 tclk0 tclk1 vco_sel0 0 vco 2 (mid input frequency range) vco 4 (low input frequency range) vco_sel1 0 gated by vco_sel0 vco (high input frequency range) pll_en 1 bypass mode, pll disabled. the input clock connects to the output dividers pll enabled. the vco output connects to the output dividers mr#/oe 1 outputs disabled (three-state) and reset of the device. during reset/output disable the pll feedback loop is open and the vco running at its minimum frequency. the device is reset by the internal power-on reset (por) circuitry during power-up. outputs enabled clk_stp# 1 qa, qb, and qc outputs disabled in low state. fb_out is not affected by clk_stp#. outputs enabled table 3. function table (bank a, b, and c) vco_sel1 vco_sel0 sela qa(4:0) selb qb(4:0) selc qc(3:0) 00 0 4 0 40 8 00 1 81 81 12 01 0 80 80 16 01 1 16 1 16 1 24 1x 0 20 20 4 1x 1 41 41 6
cy2977 5 document #: 38-07480 rev. ** page 4 of 10 table 4. function table (fb_out) vco_sel1 vco_sel0 fb_sel1 fb_sel0 fb_out 00 0 0 8 00 0 1 16 00 1 0 12 00 1 1 24 01 0 0 16 01 0 1 32 01 1 0 24 01 1 1 48 1x 0 0 4 1x 0 1 8 1x 1 0 6 1x 1 1 12 absolute maximum conditions parameter description condition min. max. unit v dd dc supply voltage ?0.3 5.5 v v dd dc operating voltage functional 2.375 3.465 v v in dc input voltage relative to v ss ?0.3 v dd + 0.3 v v out dc output voltage relative to v ss ?0.3 v dd + 0.3 v v tt output termination voltage ? v dd 2v lu latch up immunity functional 200 ? ma r ps power supply ripple ripple frequency < 100 khz ? 150 mvp-p t s temperature, storage non functional ?65 +150 c t a temperature, operating ambient functional ?40 +85 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case functional ? 23 c/w ? ja dissipation, junction to ambient functional ? 55 c/w esd h esd protection (human body model) 2000 ? volts fit failure in time manufacturing test 10 ppm
cy2977 5 document #: 38-07480 rev. ** page 5 of 10 notes: 4. driving one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, each output drives up to two 50 ? series terminated trans- mission lines. 5. inputs have pull-up or pull-down resistors that affect the input current. dc electrical specifications (v dd = 3.3v 5%, t a = ?40c to +85c) parameter description condition min. typ. max. unit v il input voltage, low lvcmos ? ? 0.8 v v ih input voltage, high lvcmos 2.0 ? v dd +0.3 v v ol output voltage, low [4] i ol = 24 ma ? ? 0.55 v i ol = 12 ma ? ? 0.30 v oh output voltage, high [4] i oh = ?24 ma 2.4 ? ? v i il input current, low [5] v il = v ss ? ? ?100 a i ih input current, high [5] v il = v dd ??100 a i dda pll supply current a vdd only ? 5 10 ma i ddq quiescent supply current all v dd pins except a vdd ?? 1ma i dd dynamic supply current outputs loaded @ 100 mhz ? 225 ? ma outputs loaded @ 200 mhz ? 290 ? c in input pin capacitance ? 4 ? pf z out output impedance 12 15 18 ? dc electrical specifications (v dd = 2.5v 5%, t a = ?40c to +85c) parameter description condition min. typ. max. unit v il input voltage, low lvcmos ? ? 0.7 v v ih input voltage, high lvcmos 1.7 ? v dd +0.3 v v ol output voltage, low [4] i ol = 15 ma ? ? 0.6 v v oh output voltage, high [4] i oh = ?15 ma 1.8 ? ? v i il input current, low [5] v il = v ss ? ? ?100 a i ih input current, high [5] v il = v dd ? ? 100 a i dda pll supply current a vdd only ? 5 10 ma i ddq quiescent supply current all v dd pins except a vdd ?? 1ma i dd dynamic supply current outputs loaded @ 100 mhz ? 135 ? ma outputs loaded @ 200 mhz ? 160 ? c in input pin capacitance ? 4 ? pf z out output impedance 14 18 22 ?
cy2977 5 document #: 38-07480 rev. ** page 6 of 10 note: 6. ac characteristics apply for parallel output termination of 50 ? to v tt . parameters are guaranteed by characterization and are not 100% tested. ac electrical specifications [6] (v dd = 2.5v 5%, t a = ?40c to +85c) parameter description condition min. typ. max. unit f vco vco frequency 200 ? 400 mhz f in input frequency 4 feedback 50 ? 100 mhz 6 feedback 33.3 ? 66.6 8 feedback 25 ? 50 12 feedback 16.7 ? 33.3 16 feedback 12.5 ? 25 24 feedback 8.3 ? 16.7 32 feedback 6.3 ? 12.5 48 feedback 4.2 ? 8.3 bypass mode (pll_en = 0) 0 ? 200 f refdc input duty cycle 25 ? 75 % t r , t f tclk input rise/falltime 0.7v to 1.7v ? ? 1.0 ns f max maximum output frequency 2 output 100 ? 200 mhz 4 output 50 ? 100 6 output 33.3 ? 66.6 8 output 25 ? 50 12 output 16.7 ? 33.3 16 output 12.5 ? 25 24 output 8.3 ? 16.7 dc output duty cycle 45 ? 55 % t r , t f output rise/fall times 0.7v to 1.8v 0.1 ? 1.0 ns t ( ) propagation delay (static phase offset) tclk to fb_in, does not include jitter ?100 ? 100 ps t sk(o) output-to-output skew skew within bank ? ? 150 ps tsk(b) bank-to-bank skew banks at same frequency ? ? 150 ps banks at different frequency ? ? 225 t plz, hz output disable time ? ? 10 ns t pzl, zh output enable time ? ? 10 ns bw pll closed loop bandwidth (?3 db) vco_sel = 0 ? 0.5 - 1.0 ? mhz vco_sel = 1 ? 1.0 - 2.0 ? t jit(cc) cycle-to-cycle jitter same frequency ? ? 150 ps multiple frequencies ? ? 300 t jit(per) period jitter ? ? 100 ps t jit( ) i/o phase jitter ? ? 150 ps t lock maximum pll lock time ? ? 1 ms
cy2977 5 document #: 38-07480 rev. ** page 7 of 10 ac electrical specifications [6] (v dd = 3.3v 5%, t a = ?40c to +85c) parameter description condition min. typ. max. unit f vco vco frequency 200 ? 500 mhz f in input frequency 4 feedback 50 ? 125 mhz 6 feedback 33.3 ? 83.3 8 feedback 25 ? 62.5 12 feedback 16.7 ? 41.6 16 feedback 12.5 ? 31.3 24 feedback 8.3 ? 20.8 32 feedback 6.3 ? 15.6 48 feedback 4.2 ? 10.4 bypass mode (pll_en = 0) 0 ? 200 f refdc input duty cycle 25 ? 75 % t r , t f tclk input rise/falltime 0.8v to 2.0v ? ? 1.0 ns f max maximum output frequency 2 output 100 ? 200 mhz 4 output 50 ? 125 6 output 33.3 ? 83.3 8 output 25 ? 62.5 12 output 16.7 ? 41.6 16 output 12.5 ? 31.3 24 output 8.3 ? 20.8 dc output duty cycle 45 ? 55 % t r , t f output rise/fall times 0.8v to 2.4v 0.1 ? 1.0 ns t ( ) propagation delay (static phase offset) tclk to fb_in, same v dd , does not include jitter ?100 ? 100 ps t sk(o) output-to-output skew skew within bank ? ? 150 ps tsk(b) bank-to-bank skew banks at same voltage, same frequency ??150ps banks at same voltage, different frequency ??225 banks at different voltage ? ? 250 t plz, hz output disable time ? ? 10 ns t pzl, zh output enable time ? ? 10 ns bw pll closed loop bandwidth (?3db) vco_sel = 0 ? 0.5 - 1.0 ? mhz vco_sel = 1 ? 1.0 - 2.0 ? t jit(cc) cycle-to-cycle jitter same frequency ? ? 150 ps multiple frequencies ? ? 300 t jit(per) period jitter ? ? 100 ps t jit( ) i/o phase jitter i/o at same v dd ??150ps t lock maximum pll lock time ? ? 1 ms
cy2977 5 document #: 38-07480 rev. ** page 8 of 10 pulse generator z = 50 ohm zo = 50 ohm vtt zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm figure 1. ac test reference for v dd = 3.3v / 2.5v t( ) lvcmos_clk fb_in vdd gnd vdd/2 vdd gnd vdd/2 figure 2. propagation delay t( ), static phase offset vdd gnd vdd/2 t p t0 dc = tp / t0 x 100% figure 3. output duty cycle (dc) t sk(o) vdd gnd vdd/2 vdd gnd vdd/2 figure 4. output-to-output skew, t sk(o)
cy2977 5 document #: 38-07480 rev. ** page 9 of 10 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress se miconductor product. nor does it convey or imply any license unde r patent or other rights. cypre ss semiconductor does not authorize its products for use as critical components in life-support system s where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimension spread aware is a trademark of cypress semiconductor corporat ion. all product and company names mentioned in this document are the trademarks of their respective holders. ordering information part number package type product flow CY29775AI 52-pin tqfp industrial, ?40 c to +85 c CY29775AIt 52-pin tqfp -tape and reel industrial, ?40 c to 85 c 52-lead thin plastic quad flat pack (10 x 10 x 1.0 mm) a52b 51-85158-**
cy2977 5 document #: 38-07480 rev. ** page 10 of 10 document history page document title:cy29775 2.5v or 3.3v, 200-mhz, 14 output zero delay buffer document #: 38-07480 rev. ecn no. issue date orig. of change description of change ** 125955 04/29/03 rgl new data sheet
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